Title :
A Block Interconnection Algorithm for Hierarchical Layout System
Author :
Fukui, Masahiro ; Yamamoto, Atsushi ; Yamaguchi, Ryuichi ; Hayama, Shigeru ; Mano, Yojiro
Author_Institution :
Semiconductor Research Center, Advanced Devices Laboratory, Matsushita Electric Industrial Co., Osaka, Japan
fDate :
5/1/1987 12:00:00 AM
Abstract :
A block interconnection algorithm for a general cell VLSI is described, which consists of a number of procedures such as a global router with signal delays taken into account, a router for power and ground, a block positioning scheme to minimize the chip size, a channel construction scheme with the use of L-shaped channels, and a grid-free channel router. The algorithm has been employed in a layout design system SMILE for general cell VLSI´s for more than one year. Some of the experimental results are also shown.
Keywords :
Algorithm design and analysis; Costs; Delay; Electric variables; Integrated circuit interconnections; Power system interconnection; Production; Routing; Switches; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.1987.1270283
