DocumentCode
915054
Title
A synthesis algorithm for reconfigurable interconnection networks
Author
Lee, Insup ; Smitley, David
Author_Institution
Dept. of Comput. & Inf. Sci., Pennsylvania Univ., Philadelphia, PA, USA
Volume
37
Issue
6
fYear
1988
fDate
6/1/1988 12:00:00 AM
Firstpage
691
Lastpage
699
Abstract
The performance of a parallel algorithm depends in part on the interconnection topology of the target parallel system. An interconnection network is called reconfigurable if its topology can be changed between different algorithm executions. Since communication patterns vary from one parallel algorithm to another, a reconfigurable network can effectively support algorithms with different communication requirements. It is shown how to generate a network topology that is optimized with respect to the communication patterns of a given task. The algorithm presented takes as input a task graph and generates as output a topology that closely matches the given input graph. The topologies generated by the algorithm are analyzed with respect to optimum interconnection topologies for the best, worst, and average cases. Simulation results verify the average-case performance prediction and confirm that, on the average, the optimum topologies are generated
Keywords
graph theory; parallel algorithms; performance evaluation; average-case performance prediction; parallel algorithm; performance; reconfigurable interconnection networks; simulation; synthesis algorithm; target parallel system; task graph; Algorithm design and analysis; Concurrent computing; Helium; Impedance matching; Multiprocessor interconnection networks; Network synthesis; Network topology; Parallel algorithms; Predictive models; Routing;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.2207
Filename
2207
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