DocumentCode :
915191
Title :
Accelerated Fault Simulation and Fault Grading in Combinational Circuits
Author :
Antreich, Kurt J. ; Schulz, Michael H.
Author_Institution :
Institute of Computer Aided Design, Department of Electrical Engineering, Technical University of Munich, Munich, Germany
Volume :
6
Issue :
5
fYear :
1987
fDate :
9/1/1987 12:00:00 AM
Firstpage :
704
Lastpage :
712
Abstract :
The principles of fault simulation and fault grading are introduced by a general description of the problem. Based upon the well-known concept of restricting fault simulation to the fanout stems and of combining it with a backward traversal inside the fanout-free regions of the circuit, proposals are presented to further accelerate fault simulation and fault grading. These proposals aim at parallel processing of patterns at all stages of the calculation procedure, at reducing the number of fanout stems for which a fault simulation has to be carried out, and at taking advantage of structural characteristics of the circuit. An experiment with a set of benchmark circuits demonstrates the efficiency of the proposed approaches.
Keywords :
Acceleration; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Costs; Proposals; Sequential analysis; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1987.1270316
Filename :
1270316
Link To Document :
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