• DocumentCode
    915294
  • Title

    Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout

  • Author

    Dai, Wei-Ming ; Kuh, Ernest S.

  • Author_Institution
    Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, CA, USA
  • Volume
    6
  • Issue
    5
  • fYear
    1987
  • fDate
    9/1/1987 12:00:00 AM
  • Firstpage
    828
  • Lastpage
    837
  • Abstract
    A new methodology for hierarchical floor planning and global routing for building block layout is presented. Unlike the traditional approach, which separates placement and global routing into two consecutive stages, our approach accomplishes both jobs simultaneously in a hierarchical fashion. The global routing problem is formulated at each level as a series of the minimum Steiner tree problem in a special class of partial 3-trees, which can be solved optimally in linear time. The floor planner with a maximum of five rooms per level has been implemented in the C language, running on a VAX 8650 under 4.3 BSD UNIX. The experimental results on examples with a large number of irregular blocks show that our approach out-performs other well-known deterministic algorithms, and gives results that are comparable to random-based algorithms but with a computing time an order of magnitude less. Due to the unique goal-oriented and pattern-directed features of our floor planner, it accepts specifications for overall aspect ratio and I/O pad positions, thus making our approach suitable for hierarchical design.
  • Keywords
    Computational complexity; Computer networks; Floors; Heat engines; Logic design; Path planning; Routing; Shape; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.1987.1270326
  • Filename
    1270326