DocumentCode :
915437
Title :
Realistic Yield Simulation for VLSIC Structural Failures
Author :
Chen, Ihao ; Strojwas, Andrzej J.
Author_Institution :
SRC-CMU Center for CAD, Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA
Volume :
6
Issue :
6
fYear :
1987
fDate :
11/1/1987 12:00:00 AM
Firstpage :
965
Lastpage :
980
Abstract :
This paper presents a methodology for determining the probability of structural failures for VLSI circuits. An analytically based approach is used to perform simulations accurately and efficiently. This approach considers the specific IC layout and accounts for most of the fault mechanisms caused by global geometrical variations and local defects. A hierarchical model is proposed to describe the defect statistics including clustering. Strict analytical methods are used to find probabilities of failure for simple layout patterns. Then, the probability of failure for macrocells are calculated hierarchically. This methodology has been implemented in a CAD tool called RYE (Realistic Yield Evaluator). To demonstrate the effectiveness of this tool, the simulation results of several examples and the CPU time comparisons with Monte Carlo methods are also presented in this paper.
Keywords :
Analytical models; Circuit analysis; Circuit faults; Circuit simulation; Failure analysis; Integrated circuit layout; Performance analysis; Probability; Statistics; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.1987.1270338
Filename :
1270338
Link To Document :
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