DocumentCode :
916111
Title :
Chips go vertical [3D IC interconnection]
Author :
Baliga, John
Volume :
41
Issue :
3
fYear :
2004
fDate :
3/1/2004 12:00:00 AM
Firstpage :
43
Lastpage :
47
Abstract :
This article describes 3D ICs. By stacking chips and directly connecting them with vertical wires, chip makers help interconnects keep up with increasing transistor speeds. A 3D IC is a stack of multiple dies with many direct connections tunneling through them, dramatically reducing global interconnect lengths and increasing the number of transistors that are within one clock cycle of each other. The key to the advantage comes from allowing wires to be routed directly between and through the chips. With this approach, the maximum global-interconnect length and the average global-interconnect length both decrease by a factor equal to the square root of the number of dies being stacked. This decreases the bottleneck effect they have on the IC´s performance by about the same factor.
Keywords :
integrated circuit interconnections; integrated circuit packaging; 3D IC interconnection; die tunneling connections; global interconnect lengths; multiple die stacked chips; vertical chips; vertical wires; Costs; Decoding; Delay; Integrated circuit interconnections; Moore´s Law; Pervasive computing; Power engineering and energy; Silicon; Transistors; Wires;
fLanguage :
English
Journal_Title :
Spectrum, IEEE
Publisher :
ieee
ISSN :
0018-9235
Type :
jour
DOI :
10.1109/MSPEC.2004.1270547
Filename :
1270547
Link To Document :
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