DocumentCode :
916203
Title :
A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications
Author :
Sohn, Ju-Ho ; Jeong-Ho Woo ; Lee, Min-Wuk ; Kim, Hye-Jung ; Woo, Ramchan ; Yoo, Hoi-Jun
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
Volume :
41
Issue :
5
fYear :
2006
fDate :
5/1/2006 12:00:00 AM
Firstpage :
1081
Lastpage :
1091
Abstract :
A 36 mm/sup 2/ graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.
Keywords :
CMOS integrated circuits; coprocessors; fixed point arithmetic; frequency synthesizers; low-power electronics; programmable circuits; reduced instruction set computing; voltage-controlled oscillators; 0.18 micron; 128 bit; 155 mW; 32 bit; 8 to 271 MHz; ARM-10 compatible RISC processor; ARM-10 coprocessor architecture; CMOS logic process; SIMD vertex shader; fixed-point programmable vertex shader; graphics processor; instruction-level power management; low power consumption; low-power rendering engine; mobile applications; pixel-level clock gating; portable 2D graphics applications; portable 3D graphics applications; programmable fixed-point single-instruction-multiple-data vertex shader; programmable frequency synthesizer; streaming multimedia processing; user-programmable vertex shading; voltage-controlled oscillator; Clocks; Engines; Frequency synthesizers; Graphics; Hardware; Reduced instruction set computing; Rendering (computer graphics); Streaming media; Two dimensional displays; Voltage-controlled oscillators; ARM co-processor; fixed-point system; frequency scaling; low-power electronics; mobile applications; programmability; rendering engine; single-instruction-multiple-data (SIMD) processing; three-dimensional graphics; vertex shader;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2006.872869
Filename :
1624397
Link To Document :
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