Title :
An AND-type match-line scheme for high-performance energy-efficient content addressable memories
Author :
Li, Hung-Yu ; Chen, Chia-Cheng ; Wang, Jinn-Shyan ; Yeh, Chingwei
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Cheng Univ., Chia-Yi, Taiwan
fDate :
5/1/2006 12:00:00 AM
Abstract :
High search speed and low energy per search are two major design goals of content-addressable memories (CAMs). In this paper, an AND-type match-line scheme is proposed to realize a high-performance energy-efficient CAM. The realized 256 × 128-b CAM macro, based on a 0.18-μm 1.8-V CMOS process, achieves a 2.1-ns search time. When both the stored and search data are generated from an on-chip 4 × 32-b LFSR with the same seed, the measured energy is 2.33-fJ/bit/search.
Keywords :
CMOS memory circuits; content-addressable storage; high-speed integrated circuits; 0.18 micron; 1.8 V; 2.1 ns; AND-type match-line scheme; CAM; CMOS process; LFSR; content-addressable memories; energy efficiency; Associative memory; CADCAM; CMOS process; Cams; Circuits; Computer aided manufacturing; Energy consumption; Energy efficiency; Table lookup; Voltage; Content-addressable memory (CAM); low power; match line scheme;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.872719
