A RAM based CMOS histogrammer integrated circuit

Author

Slorach, F. ; Alsford, J.R.

Author_Institution

Rutherford Appleton Lab., Chilton, UK

Volume

35

Issue

1

fYear

1988

Firstpage

209

Lastpage

212

Abstract

A histogramming integrated circuit has been designed with 256 24-bit cells. The pipelined RAM-based architecture has been designed to give histogram capture rates of at least 8 MHz. The chip is capable of histogramming an entire 512*512 image with an 8-bit gray level in real time and is fully cascadable for increased histogram resolution or capacity. The RAM is accessible for random read/write operations through the 24-bit data and 8-bit address busses. Additional features include global thresholding, sequential read/clear, and a simple self-test on the RAM. The chip was designed using an integrated design system with a ramcell compiler and is being fabricated in a 2- mu m CMOS technology.<>

Keywords

CMOS integrated circuits; integrated memory circuits; random-access storage; RAM based CMOS histogrammer integrated circuit; capacity; global thresholding; increased histogram resolution; ramcell compiler; self-test; sequential read/clear; Automatic testing; CMOS integrated circuits; CMOS technology; Counting circuits; Frequency; Histograms; Image processing; Image resolution; Laboratories; Pixel;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.12709

Filename

12709