Hardware evaluation of mathematical functions

The paper presents a family of algorithms for evaluating the elementary mathematical functions including division, sine, cosine, tangent, arctangent, logarithm, exponential and square root. The algorithms are based on continued products and continued sums, and generate the sum on a 2-bit-at-a-time basis. The only operations required are shifting, adding, subtracting and recall of prestored constants. Consequently, the method is suitable for hardware implementation, and two designs are presented. The faster design can generate a 64-bit result in under 1 ¿¿s for most of the functions, and under 2 ¿¿S for the remainder, when using ECL technology of the F100K type. The other design is based on a pipelined structure and is approximately 40% slower and cheaper. The performance of both designs compares favourably with that of a hardwired polynomial evaluation based on Homer´s scheme when using a 300 ns 64- by 64-bit multiplier. Such a design is between 35% and 130% slower than the pipelined version depending upon the function evaluated, yet only 30% cheaper.