Analysis and synthesis of weighted-sum functions

Author

Sasao, Tsutomu

Author_Institution

Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan

Volume

25

Issue

5

fYear

2006

fDate

5/1/2006 12:00:00 AM

Firstpage

789

Lastpage

796

Abstract

A weighted-sum (WS) function computes the sum of selected integers. This paper considers a design method for WS functions by look-up table (LUT) cascades. In particular, it derives upper bounds on the column multiplicities of decomposition charts for WS functions. From these, the size of LUT cascades that realize WS functions can be estimated. The arithmetic decomposition of a WS function is also shown. With this method, a WS function can be implemented with cascades and adders.

Keywords

adders; binary decision diagrams; digital arithmetic; table lookup; FPGA; adders; arithmetic decomposition; binary decision diagram; column multiplicity; complexity of logic functions; decomposition charts; digital filter; distributed arithmetic; functional decomposition; look-up table cascade; radix converter; selected integer sum; symmetric function; threshold function; weighted-sum functions; Adders; Arithmetic; Counting circuits; Design methodology; Field programmable gate arrays; Mathematical model; Matrix decomposition; Programmable logic arrays; Table lookup; Upper bound; Binary decision diagram; LUT cascades; column multiplicity; complexity of logic functions; digital filter; distributed arithmetic; field programmable gate array (FPGA); functional decomposition; radix converter; symmetric function; threshold function;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2006.870407

Filename

1624513