Hierarchical synthesis of complex DSP functions using IRIS

A "white box" design methodology, which deals with hierarchical synthesis issues by providing a bridge between a high-level algorithm representation and lower level design tools, is presented. It illustrates tradeoffs when dealing with designs in a hierarchical and flattened manner. An enhanced Minnesota architectural synthesis scheduling algorithm is given, which gives highly efficient field programmable gate array solutions by providing access to parameterized expressions for datapath latencies and is applied to normalized lattice and delayed least mean square filter examples.