Title :
Poor man´s gate arrays-logic cell arrays
Author :
Brandenburg, G. ; Gorschütz, U. ; Müller, K.D.
Author_Institution :
Zentrallabor fur Elektronik, KFA Julich GmbH, West Germany
Abstract :
For simple applications, where gate arrays are too expensive and the turnaround time for design, production, and changes is not acceptable, logic cell arrays are suggested as an alternative. Logic cell arrays store the gate-interconnecting information in on-chip memory cells and can therefore be loaded or reloaded within several milliseconds. As an example, the design of an interface for a neutron time-of-flight multidetector arrangement is described, and advantages and disadvantages of the approach are discussed.<>
Keywords :
cellular arrays; integrated logic circuits; neutron detection and measurement; gate arrays; gate-interconnecting information; interface; logic cell arrays; neutron time-of-flight multidetector arrangement; on-chip memory cells; Clocks; Delay; Flip-flops; Joining processes; Logic arrays; Logic design; Logic gates; Logic testing; Neutrons; Production;
Journal_Title :
Nuclear Science, IEEE Transactions on
