• DocumentCode
    917536
  • Title

    A Highly Scalable GALS Crossbar Using Token Ring Arbitration

  • Author

    Singh, Tejpal ; Taubin, Alexander

  • Author_Institution
    Intel Massachusetts, Hudson
  • Volume
    24
  • Issue
    5
  • fYear
    2007
  • Firstpage
    464
  • Lastpage
    472
  • Abstract
    With increases in die size and clock frequency, driving signals across dies is becoming increasingly more difficult. To reduce clock skew and power, the general trend is to use multiple clock domains on a single die, making both synchronous and asynchronous interclock domain communication possible. The 2005 International Technology Roadmap for Semiconductors states that asynchronous global signaling is required to handle multiple clock domains. According to the ITRS, the globally asynchronous, locally synchronous (GALS) methodology should address this problem. This methodology enables the use of a clocked design for smaller-scale functional units, and this has been the standard approach in industry. The GALS methodology also makes it possible to connect synchronous functional units using robust asynchronous interconnects. The efficient design of an asynchronous crossbar is one of the most promising implementations of the GALS methodology. In this article, we present a low-latency crossbar that uses a distributed arbitration mechanism in the form of token rings. We further improve the latency of this implementation by implementing asynchronous-to-synchronous and synchronous-to-asynchronous interface logic using bidirectional signals. These signals serve as requests and acknowledges, and they exhibit a very fast GasP-like implementation - although, unlike GasP, this implementation is not self-resetting.
  • Keywords
    asynchronous circuits; clocks; logic design; logic testing; GALS methodology; asynchronous-to-synchronous interface logic; bidirectional signals; distributed arbitration mechanism; globally asynchronous locally synchronous method; highly scalable GALS crossbar; low-latency crossbar; multiple clock domains; ring arbitration; synchronous-to-asynchronous interface logic; token-ring-based asynchronous crossbar; Circuit testing; Clocks; Delay; Fabrics; Frequency; Joining processes; Logic; Robustness; Scalability; Token networks; arbitration; crossbar design; latency; scalability; token rings;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2007.150
  • Filename
    4338467