DocumentCode
917544
Title
Suppression of parasitic bipolar effects in thin-film SOI transistors
Author
Armstrong, G.A. ; French, W.D.
Author_Institution
Dept. of Electr. & Electron. Eng., Queen´´s Univ., Belfast, UK
Volume
13
Issue
4
fYear
1992
fDate
4/1/1992 12:00:00 AM
Firstpage
198
Lastpage
200
Abstract
In order to correctly estimate the bipolar holding voltage of thin-film SOI transistors with submicrometer gate lengths, it is necessary to obtain the correct balance between the bipolar current gain and impact ionization. The bipolar current gain was found to be strongly dependent upon bandgap narrowing in the heavily doped source, while impact ionization may be most accurately modeled with a nonlocal ballistic model employing a composite electron mean-free path of 9.2 nm. Simulation with the improved models suggests that a reduction in the lateral electric field of the n/sup -/ drain region, and hence an increased bipolar holding voltage, may be achieved by using ultrathin highly doped SOI films. For a 0.5- mu m gate length, a maximum holding voltage in excess of 6 V has been simulated.<>
Keywords
carrier mean free path; impact ionisation; insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; thin film transistors; MOSFET; bandgap narrowing; bipolar current gain; bipolar holding voltage; composite electron mean-free path; heavily doped source; impact ionization; lateral electric field; n/sup -/ drain region; nonlocal ballistic model; parasitic bipolar effects; simulation; submicrometer gate lengths; thin-film SOI transistors; ultrathin highly doped SOI films; Doping; Impact ionization; MOSFETs; Photonic band gap; Predictive models; Semiconductor process modeling; Semiconductor thin films; Silicon on insulator technology; Thin film transistors; Voltage;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.145019
Filename
145019
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