Title :
Increasing encoding efficiency of LFSR reseeding-based test compression
Author :
Kim, Hong-Sik ; Kang, Sungho
Author_Institution :
Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fDate :
5/1/2006 12:00:00 AM
Abstract :
A new methodology to increase the encoding efficiency of test compression based on linear feedback shift registers (LFSRs) is proposed. The proposed method combines LFSR reseeding and bit fixing. Deterministic test patterns tend to have a biased probability of the logic value 1 or 0 at each primary input. If such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then the amount of data to be encoded by the LFSR will be considerably reduced. Additionally, in order to reduce the encoded data volume much further, a variable degree of the LFSR polynomial is employed. In the variable-degree LFSR scheme, a test cube with less specified bits is encoded with an LFSR polynomial of lower degree, while a test cube with more specified bits is encoded with an LFSR polynomial of higher degree. Experimental results for the larger ISCAS 89 benchmark circuits show that the proposed scheme can increase the encoding efficiency with little hardware overhead compared to previous schemes.
Keywords :
encoding; integrated circuit testing; logic testing; polynomials; shift registers; LFSR polynomial; LFSR reseeding; bit fixing; combinational logic; deterministic test patterns; encoding efficiency; linear feedback shift registers; test compression; variable-degree LFSR scheme; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Design for testability; Encoding; Linear feedback shift registers; Logic testing; Polynomials; Built-in self-test; linear feedback shift register (LFSR) reseeding; scan testing; test compression;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2005.855977