DocumentCode :
917858
Title :
Multistage-based switching fabrics for scalable routers
Author :
Tzeng, Nian-Feng
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Louisiana, Lafayette, LA, USA
Volume :
15
Issue :
4
fYear :
2004
fDate :
4/1/2004 12:00:00 AM
Firstpage :
304
Lastpage :
318
Abstract :
Rapidly growing demand for high-speed networks has prompted the investigation into scalable routers that are capable of forwarding data at the aggregate rate of multiterabits per second. Such a router contains many line cards (LCs) for admitting external links of various speeds. Those LCs are interconnected by a switching fabric to provide paths for packets to travel from arrival LCs to their respective departure LCs. The switching fabric employed in a router dictates the scalability and the overall performance of the router. It is thus crucial for future multiterabit routers to incorporate scalable switching fabrics capable of interconnecting large numbers of LCs. This work considers switching fabrics with distributed packet routing to achieve high scalability and low costs. Our fabrics are based on a multistage structure with different recirculation designs, where adjacent stages are interconnected according to the indirect n-cube connection style. They all compare favorably with an earlier multistage-based counterpart according to extensive simulation, in terms of performance measures of interest and hardware complexity. When queues are incorporated in the output ports of switching elements (SEs), the total number of stages required in our proposed fabrics to achieve a given performance level can be reduced substantially. The performance of those fabrics with output queues is evaluated under different "speedups" of the queues, where the speedup is the operating clock rate ratio of that at the SE core to that over external links. It is found via our simulation results that a small speedup of two is adequate for buffered switching fabrics comprising 4×8 SEs to deliver better performance than their nonbuffered counterparts with 50 percent more stages of SEs, when the fabric size is 256. The buffered switching fabrics under different traffic patterns are evaluated and discussed as well. Being scalable and of low costs, the proposed switching fabrics are ideally suitable for routers with large numbers of LCs.
Keywords :
distributed shared memory systems; multistage interconnection networks; network routing; packet switching; LC; SE; distributed packet routing; line cards; multistage based switching fabrics; recirculation design; scalable router; switching element; Aggregates; Clocks; Costs; Fabrics; Hardware; High-speed networks; Packet switching; Routing; Scalability; Traffic control;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/TPDS.2004.1271180
Filename :
1271180
Link To Document :
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