COMELOT: a computer-aided measure for logic testability

This paper describes the theory and application of a testability assessment program, called CAMELOT, which has been developed for British Telecom. The program is intended for use as an interactive design aid, the testability predictions produced allowing the designer to make the best use of the range of testability improvement techniques available. CAMELOT uses a model of the test generation process to calculate controllability and observability values for each circuit node. These values measure the ease with which the node concerned can be set to a desired logic level and the ease with which its state can be observed respectively. The calculations take into account the possibility that a stored state device may have either an initialisation requirement or transient states. By combining the sets of values calculated, testability estimates can be produced for each circuit node and for the circuit as a whole. The paper describes the concepts of CAMELOT, relates it to other testability measures that have been described in the open literature and gives examples of its use.