Title :
A new bit-serial systolic multiplier over GF(2m)
Author_Institution :
Comput. Sci. Lab., Australian Nat. Univ., Canberra, ACT, Australia
fDate :
6/1/1988 12:00:00 AM
Abstract :
A bit-serial systolic array has been developed to computer multiplications over GF(2m). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal
Keywords :
VLSI; cellular arrays; logic design; bit-serial systolic multiplier; linear systolic array; Algorithm design and analysis; Arithmetic; Computer architecture; Control systems; Equations; Galois fields; Polynomials; Signal design; Systolic arrays; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
