• DocumentCode
    918787
  • Title

    A new bit-serial systolic multiplier over GF(2m)

  • Author

    Zhou, B.B.

  • Author_Institution
    Comput. Sci. Lab., Australian Nat. Univ., Canberra, ACT, Australia
  • Volume
    37
  • Issue
    6
  • fYear
    1988
  • fDate
    6/1/1988 12:00:00 AM
  • Firstpage
    749
  • Lastpage
    751
  • Abstract
    A bit-serial systolic array has been developed to computer multiplications over GF(2m). In contrast to a previously designed systolic multiplier, this algorithm allows the input elements to center a linear systolic array in the same order, and the system only requires one control signal
  • Keywords
    VLSI; cellular arrays; logic design; bit-serial systolic multiplier; linear systolic array; Algorithm design and analysis; Arithmetic; Computer architecture; Control systems; Equations; Galois fields; Polynomials; Signal design; Systolic arrays; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.2216
  • Filename
    2216
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=918787