A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment

As VLSI technology enters the nanoscale regime, the interconnect delay becomes the bottleneck of circuit performance. Compared with gate delays, wires are becoming increasingly resistive, making it more difficult to propagate signals across the chip. However, more advanced technologies (65 and 45 nm) provide relief as the number of metal layers continues to increase. The wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. This provides an entirely new dimension to the traditional wire-sizing problem, namely, layer assignment for efficient timing closure. Assigning all wires to thick metals improves timing; however, the routability of the design may be hurt. The challenge is to assign a minimal amount of wires to thick metals to meet timing constraints. In this brief, the minimum cost layer assignment problem is proven to be NP-complete. As a theoretical solution for NP-complete problems, a fully polynomial-time approximation scheme is proposed. The new algorithm can approximate the optimal layer assignment solution by a factor of 1 + isin in O(m log log M ldrn ³ isin²) time for 0 < isin < 1, where n is the number of nodes in the tree, m is the number of routing layers, and M is the maximum cost ratio among layers. This work presents the first theoretical advance for the timing-driven minimum cost layer assignment problem. In addition to its theoretical guarantee, the new algorithm is highly practical. Our experiments on 500 industrial test cases demonstrate that the new algorithm can run 2times faster than the optimal dynamic programming algorithm, with only 2% additional wire.