Title :
Suitability of metal gate stacks for low-power and high-performance applications: impact of carrier confinement
Author :
Kumar, Arvind ; Solomon, Paul Michael
Author_Institution :
Thomas J. Watson Res. Center, IBM Semicond. R&D Center, Yorktown Heights, NY, USA
fDate :
5/1/2006 12:00:00 AM
Abstract :
A simulation study is carried out to assess the competitiveness of metal gate stacks for low-power and high-performance technologies using realistic oxynitride and high-permittivity gate dielectric stacks having insulator leakages appropriate for each application. In the first part of this paper, the metal-gate work function is fixed at a value near midgap. For this value of work function, the performance (obtained from mixed-mode simulations of inverter delay chains) of metal gate stacks is found to exceed that of polysilicon gate stacks for low-power applications, but to be uncompetitive for high-performance applications. Both of these observations are explained by understanding the role of carrier confinement determined by the channel doping required for each application. In the second part of this paper, the metal-gate work function is allowed to vary in order to obtain the optimal work-function ranges for each application. Metal gate stacks are shown to be especially suitable for low-power applications over a wide range of possible work functions, with optimal performance away from the band edges. For high-performance applications, work functions near the band edges yield the best performance, but significant gains compared to polysilicon-gated devices are found only when additional scaling is achieved through a use of a high-permittivity gate insulator.
Keywords :
dielectric materials; electron traps; high-k dielectric thin films; low-power electronics; permittivity; MOS devices; carrier confinement; channel doping; high permittivity gate dielectric stacks; high-performance applications; high-permittivity gate insulator; insulator leakages; inverter delay chains; low-power applications; metal gate stacks; metal-gate work function; mixed-mode simulations; polysilicon gate stacks; realistic oxynitride; Appropriate technology; Carrier confinement; Degradation; Dielectrics; Doping; Insulation; Leakage current; Metal-insulator structures; Semiconductor impurities; Threshold voltage; MOS devices; semiconductor device modeling; work function;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2006.872883