Jitter Challenges and Reduction Techniques at 10 Gb/s and Beyond

Author

Li, Mike Peng

Author_Institution

Altera, San Jose, CA

Volume

32

Issue

2

fYear

2009

fDate

5/1/2009 12:00:00 AM

Firstpage

290

Lastpage

297

Abstract

The bandwidths of high-speed input/output (I/O) links keep increasing to meet the ever-growing demands for high-speed communications. The data rates for the leading edge high-speed I/O standards have already increased to around 10 Gb/s, including 10 GB Ethernet (GBE, 10 Gb/s, or 4 times 10.3125 Gb/s, and 10 times10.3125 Gb/s for Ethernet 40 G/100 G), 8 times fibre channel (8.5 Gb/s), and PCI Express Gen 3 (at 8 Gb/s). At those data rates, the total available timing budget become less, data-dependent jitter gets severe, and jitter amplification becomes significant. This paper focuses on these jitter challenges and associated mitigation/reduction technologies, including jitter tracking via clock recovery, eye-opening via equalizations, and DCD cancellation via delay elements to avoid jitter amplification.

Keywords

equalisers; jitter; local area networks; synchronisation; telecommunication links; DCD cancellation; Ethernet; PCI Express Gen 3; ata-dependent jitter; clock recovery; data rate; equalization; fibre channel; high-speed I/O standard; high-speed communication; high-speed input/output links; jitter amplification; jitter tracking; mitigation technology; reduction technology; Bandwidth; Bit error rate; CMOS technology; Clocks; Ethernet networks; Integrated circuit technology; Intersymbol interference; Optical fibers; Timing jitter; Transmitters; CMOS analog integrated circuits; CMOS digital integrated circuits; CMOS integrated circuits; communication system performance;

fLanguage

English

Journal_Title

Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1521-3323

Type

jour

DOI

10.1109/TADVP.2009.2012432

Filename

4982896