• DocumentCode
    920260
  • Title

    Field-effect-transistor-bridge multiplier-divider

  • Author

    Abu-Zeid, M.M. ; Groendijk, H.

  • Author_Institution
    Eindhoven University of Technology, Eindhoven, Netherlands
  • Volume
    8
  • Issue
    24
  • fYear
    1972
  • Firstpage
    591
  • Lastpage
    592
  • Abstract
    A description is given of a 4-quadrant temperature-compensated multiplier-divider circuit in the form of a self-balancing f.e.t. bridge consisting of two matched f.e.t. pairs.
  • Keywords
    bridge circuits; dividing circuits; field effect transistors; multiplying circuits; 4 quadrant; multiplier/divider circuit; self balancing FET bridge; temperature compensated; two matched FET pairs;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19720429
  • Filename
    4235895
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=920260