• DocumentCode
    920680
  • Title

    Pipeline array for square-root extraction

  • Author

    Majithia, J.C.

  • Author_Institution
    University of Waterloo, Department of Electrical Engineering, Faculty of Engineering, Waterloo, Canada
  • Volume
    9
  • Issue
    1
  • fYear
    1973
  • Firstpage
    4
  • Lastpage
    5
  • Abstract
    Pipelining an arithmetic process is a well known technique for improving the computation speed of the arithmetic algorithm. In the letter is proposed a pipeline version of the array for the extraction of square roots of binary numbers. It is shown that a significant speed improvement (on a throughout basis) can result by this modification of the conventional logic arrays.
  • Keywords
    cellular arrays; digital arithmetic; logic circuits; arithmetic process pipelining; cellular arrays; conventional logic arrays; square root extraction;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19730003
  • Filename
    4235937
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=920680