Title :
A 286 MHz 64-b floating point multiplier with enhanced CG operation
Author :
Makino, Hiroshi ; Suzuki, Hiroaki ; Morinaka, Hiroyuki ; Nakase, Yasunobu ; Mashiko, Koichiro ; Sumi, Tadashi
Author_Institution :
Syst. LSI Lab., Mitsubishi Electr. Corp., Itami, Japan
fDate :
4/1/1996 12:00:00 AM
Abstract :
This paper presents a high speed 64-b floating point (FP) multiplier that has a useful function for computer graphics (CG). The critical path delay is minimized by using high speed logic gates and limiting the stage number of series transmission gates (TGs). The high speed redundant binary architecture is applied to the multiplication of significands. This FP multiplier has a special function of “CG multiplication” that directly multiplies a pixel data by an FP data. This multiplier was fabricated by 0.5-μm CMOS technology with triple-level metal of interconnection. The active area size is 4.2×5.1 mm2. The operating cycle time is 3.5 ns at the supply voltage of 3.3 V, which corresponds to the frequency of 286 MHz. Implementation of CG multiplication increases the transistor count only 4%. Also, CG multiplication has no effect on the delay in the critical path
Keywords :
CMOS digital integrated circuits; computer graphics; floating point arithmetic; multiplying circuits; 0.5 micron; 286 MHz; 3.3 V; 3.5 ns; 64 bit; CMOS technology; active area size; computer graphics operation; critical path delay; floating point multiplier; high speed logic gates; pixel data; redundant binary architecture; series transmission gates; significand multiplication; transistor count; triple-level metal; CMOS logic circuits; CMOS technology; Character generation; Circuit testing; Computer architecture; Computer graphics; Delay; Delay effects; Frequency; Integrated circuit interconnections; Logic circuits; Logic gates; Microprocessors; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
