An efficient charge recovery logic circuit

Author

Moon, Yong ; Jeong, Deog-Kyoon

Author_Institution

Inter-Univ. Semicond. Res. Centre, Seoul Nat. Univ., South Korea

Volume

31

Issue

4

fYear

1996

fDate

4/1/1996 12:00:00 AM

Firstpage

514

Lastpage

522

Abstract

Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows four to six times power reduction with a practical loading and operation frequency range. An inductor-based supply clock generation circuit is proposed. Circuits are designed using 1.0-μm CMOS technology with a reduced threshold voltage of 0.2 V

Keywords

CMOS logic circuits; adders; carry logic; logic gates; pipeline arithmetic; 0.2 V; 1.0 micron; CMOS technology; carry lookahead adder; charge recovery logic circuit; efficient charge recovery logic; inductor-based supply clock generation circuit; inverter chain; low-energy adiabatic logic circuit; operation frequency range; pipelined structure; power reduction; threshold voltage; Adders; CMOS logic circuits; CMOS technology; Clocks; Energy loss; Frequency; Inverters; Logic circuits; Moon; Power supplies; Semiconductor diodes; Switches; Threshold voltage; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.499727

Filename

499727