Yield enhancement realised for analogue integrated filters by design techniques

In the fabrication of analogue integrated circuits the yield depends on the tolerances and defect density in mask generation and device fabrication. Yield optimisation, therefore, has to resolve two conflicting requirements. Whereas to reduce the influence of tolerances the device area has to be large, the larger the device area chosen, the higher will be the possible defect number. To determine the optimum device area with respect to yield in the fabrication of CCD transversal filters, the tolerances in mask generation and fabrication have first to be analysed. Tolerances that are constant in a device can be eliminated by `design cleverness¿. The way in which the influence of statistical tolerances can be reduced by design centering will be demonstrated with reference to an implemented device. To determine the total yield it is further necessary to take into account the influence of defects. The optimum device area from the aspect of yield can then be determined as a function of both tolerance and defect density.