Title :
A BiCMOS programmable frequency divider
Author :
Choy, Chiu-Sing ; Ho, Chun-ying ; Lunn, Gerald ; Lin, Benny ; Fung, Gary
Author_Institution :
Dept. of Electr. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
fDate :
3/1/1992 12:00:00 AM
Abstract :
A BiCMOS programmable frequency divider which is a major functional block of a frequency synthesis IC based on a phased-locked loop is described. Innovative techniques are demonstrated to solve many incompatibility problems between ECL and CMOS techniques. It is shown that a similar concept can be applied to other high-speed designs. The frequency divider has 15 stages and operates at 165 MHz. It occupies 0.375 mm2 of die area, which is only a third of what is required in an all-bipolar version. Power consumption is about 55 mW, which is 80% of that of the all-bipolar version
Keywords :
BIMOS integrated circuits; emitter-coupled logic; frequency dividers; integrated logic circuits; 165 MHz; 55 mW; BiCMOS; CMOS; ECL; frequency synthesis IC; high-speed designs; incompatibility problems; phased-locked loop; programmable frequency divider; BiCMOS integrated circuits; CMOS process; CMOS technology; Frequency conversion; Frequency synthesizers; Integrated circuit synthesis; Integrated circuit technology; MOSFETs; Phase locked loops; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
