Title :
A 1.5-ns access time, 78-μm2 memory-cell size, 64-kb ECL-CMOS SRAM
Author :
Yamaguchi, Kunihiko ; Nambu, Hiroaki ; Kanetani, Kazuo ; Idei, Youji ; Homma, Noriyuki ; Hiramoto, Toshiro ; Tamba, Nobuo ; Watanabe, Kunihiko ; Odaka, Masanori ; Ikeda, Takahide ; Ohhata, Kenichi ; Sakurai, Yoshiaki
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
2/1/1992 12:00:00 AM
Abstract :
A 1.5-ns access time, 78-μm2 memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers
Keywords :
BIMOS integrated circuits; SRAM chips; cellular arrays; emitter-coupled logic; 1.5 ns; 64 kbit; BiCMOS circuit; CMOS cell arrays; ECL word drivers; ECL write circuits; ECL-CMOS SRAM; high-density SRAMs; high-performance device; memory-cell; soft-error immunity; BiCMOS integrated circuits; CMOS memory circuits; Cache storage; Delay; Driver circuits; High performance computing; Laboratories; Random access memory; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
