A high-speed CMOS comparator with 8-b resolution

Author

Yin, G.M. ; Eynde, F. Op´t ; Sansen, W.

Author_Institution

Dept. Elektrotechniek, Katholieke Univ. Leuven, Heverlee, Belgium

Volume

27

Issue

2

fYear

1992

fDate

2/1/1992 12:00:00 AM

Firstpage

208

Lastpage

211

Abstract

A comparator consisting of a differential input stage, two regenerative flip-flops, and an S-R latch is presented. No offset cancellation is exploited, which reduces the power consumption as well as the die area and increases the comparison speed. An experimental version of the comparator has been integrated in a standard double-poly double-metal 1.5-μm n-well process with a die area of only 140×100 μm². This circuit, operating under a +2.5/-2.5-V power supply, performs comparison to a precision of 8 b with a symmetrical input dynamic range of 2.5 V (therefore ±0.5 LSB resolution is equal to ±4.9 mV)

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); flip-flops; integrated logic circuits; -2.5 V; 1.5 micron; 2.5 V; 8 bit resolution; ADC application; S-R latch; differential input stage; double-poly double-metal; high-speed CMOS comparator; n-well process; regenerative flip-flops; CMOS technology; Circuits; Clocks; Dynamic range; Energy consumption; Flip-flops; Latches; Power supplies; Switches; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.127344

Filename

127344