• DocumentCode
    922291
  • Title

    Fast high-input-impedance unity-gain buffer stage

  • Author

    Hart, B.L. ; Barker, R.W.J.

  • Author_Institution
    North-East London Polytechnic, Department of Electrical Engineering, Dagenham, UK
  • Volume
    9
  • Issue
    10
  • fYear
    1973
  • Firstpage
    223
  • Lastpage
    224
  • Abstract
    The interconnection of a monolithic matched-f.e.t. pair and a high-frequency bipolar-transistor array permits the design of a fast high-input-impedance unity-gain buffer stage that does not employ passive components. Typical performance data are: input direct bias current <50 pA, output impedance <50 ¿, power consumption <60 mW.
  • Keywords
    buffer circuits; FET; HF; bipolar transistors; buffer circuits;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19730162
  • Filename
    4236104
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=922291