A multiplier chip with multiple-valued bidirectional current-mode logic circuits

Author

Kameyama, Michitaka ; Kawahito, Shoji ; Higuchi, Tatsuo

Author_Institution

Tohoku Univ., Japan

Volume

21

Issue

4

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

43

Lastpage

56

Abstract

A description is given of a 32*32-bit signed digit multiplier implemented with multiple-valued, bidirectional, current-mode circuits and based on two-microcomputer complementary metal-oxide-semiconductor technology. The multiplier can perform 32-bit two´s-complement multiplication with three-stage SD full adders using a binary-tree addition scheme The effective multiplier size in the chip and the power dissipation are almost half that of the corresponding binary CMOS multiplier. The multiply time is comparable to that of the fastest binary multiplier. These results establish the effectiveness of the technology for future very large scale integration.<>

Keywords

CMOS integrated circuits; VLSI; many-valued logics; multiplying circuits; 32-bit two´s-complement multiplication; binary CMOS multiplier; binary-tree addition scheme; multiple-valued bidirectional current-mode logic circuits; multiplier chip; multiply time; power dissipation; signed digit multiplier; three-stage SD full adders; two-microcomputer complementary metal-oxide-semiconductor technology; very large scale integration; Adders; Arithmetic; CMOS technology; Data processing; Encoding; Hardware; Integrated circuit interconnections; Large scale integration; Logic circuits; Very large scale integration;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.50

Filename

50