Title :
Corrigendum to ´synthetic traces for trace-driven simulation of cache memories´
Author :
Thiebaut, D. ; Wolf, Joel ; Stone, Harold
Author_Institution :
Dept. of Comput. Sci., Smith Coll., Northampton, MA, USA
fDate :
5/1/1993 12:00:00 AM
Abstract :
Three errors appearing in the above-tilted paper by D. Thiebaut, J. Wolf, and H. Stone (see ibid., vol.41, no.4, p.388-410, 1992) are corrected. They were introduced during the revision process and do not affect the results.<>
Keywords :
buffer storage; system monitoring; virtual storage; cache memories; synthetic traces; trace-driven simulation; Algorithm design and analysis; Computer architecture; Fault detection; Fault diagnosis; Fault tolerance; Fault tolerant systems; Multiprocessing systems; System testing; Upper bound;
Journal_Title :
Computers, IEEE Transactions on
