Title :
Two schemes for detecting CMOS analog faults
Author :
Chang, Tsin-Yuan ; Wang, Cheng-Chi ; Hsu, Jain-Bean
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fDate :
2/1/1992 12:00:00 AM
Abstract :
A design-for-testability scheme for detecting CMOS analog faults was reported by Favalli et al. (see ibid., vol.25, no.5, p.1239-46, 1990). The authors propose two alternative designs, one for small circuits and another for large circuits, which require significantly less area overhead (about 1/4 to 1/3) than that of Favalli´s design. With the proposed modification in the first design, the untestable problem, which occurred in Favalli´s design, can be alleviated. Furthermore, the proposed schemes are also fit to be implemented in VLSI circuits
Keywords :
CMOS integrated circuits; VLSI; fault location; integrated circuit testing; integrated logic circuits; logic design; logic testing; CMOS analog faults; VLSI circuits; complementary logic; design-for-testability scheme; large circuits; small circuits; Circuit faults; Circuit testing; Design for testability; Electrical fault detection; Fault detection; Logic testing; MOSFETs; Solid state circuit design; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
