Title :
A 7-mask CMOS process with selective oxide deposition
Author :
Horiuchi, Tadahiko ; Kanba, Kouji ; Homma, Tetsuya ; Murao, Yukinobu ; Okumura, Koichiro
Author_Institution :
NEC Corp., Kanagawa, Japan
fDate :
8/1/1993 12:00:00 AM
Abstract :
A seven mask CMOS process using liquid phase oxide deposition which has selectivity against photoresist is described. The process modules for self-aligned well and one-mask LDD formation are developed. The features of the process are: (1) short TAT (7 masks to first metallization), (2) self-aligned twin retrograde wells with 40% reduction of the p+-n+ spacing compared to conventional wells, and (3) optimal LDD design using different sidewall spacer width for n- and p-channel MOSFETs giving a 10% larger on-current for p-channel MOSFETs compared to a conventional process
Keywords :
CMOS integrated circuits; integrated circuit technology; masks; liquid phase oxide deposition; one-mask LDD formation; optimal LDD design; p-channel MOSFETs; process modules; selective oxide deposition; self-aligned twin retrograde wells; self-aligned well; seven mask CMOS process; short TAT; sidewall spacer width; CMOS process; CMOS technology; Chemicals; Hafnium; Implants; Impurities; MOSFETs; Metallization; National electric code; Resists;
Journal_Title :
Electron Devices, IEEE Transactions on
