Title :
V groove m.o.s. transistor technology
Author :
Holmes, F.E. ; Salama, C.A.T.
Author_Institution :
University of Toronto, Department of Electrical Engineering, Toronto, Canada
Abstract :
An m.o.s. transistor structure in which the channel is defined by preferential etching of the silicon is described. The fabrication technology involves either a 3- or 4-mask process, and results in very-short-channel devices, using noncritical alignment tolerances. Experimental results obtained on the fabricated devices are presented, and possible uses of the technology are described.
Keywords :
field effect transistors; integrated circuit production; monolithic integrated circuits; Sr; V groove MOST; preferential etching;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19730333
