Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In_0.53Ga_0.47As/InP double heterojunction bipolar transistors (DHBTs) employing an N⁺ subcollector and N⁺ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C_cb associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N⁺ subcollector that lies underneath the base ohmic contact, as well as compensate the ∼1-7×10^-7 C/cm² surface charge at the interface between the indium phosphide (InP) substrate and the N^$collector drift layer. By implanting the subcollector, C_cb associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C_cb by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f_τ and 403-GHz f_max. The dc current gain β≈38, BV_ceo=6.0 V, BV_cbo=5.4 V, and I_cbo<50 pA at V_cb=0.3 V.