A VLIW architecture for a trace scheduling compiler

Author

Colwell, R.P. ; Nix, Robert P. ; Donnell, John J O ; Papworth, David B. ; Rodman, Paul K.

Author_Institution

Multiflow Comput., Branford, CT, USA

Volume

37

Issue

8

fYear

1988

fDate

8/1/1988 12:00:00 AM

Firstpage

967

Lastpage

979

Abstract

A VLIW (very long instruction word) architecture machine called the TRACE has been built along with its companion Trace Scheduling compacting compiler. This machine has three hardware configurations, capable of executing 7, 14, or 28 operations simultaneously. The `seven-wide´ achieves a performance improvement of a factor of five or six for a wide range of scientific code, compared to machines of higher cost and fast chip implementation technology (such as the VAX 8700). The TRACE extends some basic reduced-instruction-set computer (RISC) precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for run-time resource usage). The authors discuss the design of this machine and present some initial performance results

Keywords

computer architecture; program compilers; scheduling; TRACE; VLIW architecture; performance results; run-time resource usage; trace scheduling compiler; very long instruction word; Computer architecture; Concurrent computing; Costs; Hardware; Large-scale systems; Microarchitecture; Parallel processing; Processor scheduling; Trademarks; VLIW;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.2247

Filename

2247