Digital signal processing schemes for efficient interpolation and decimation

In this paper a new structure for sampling rate alteration is presented in which efficiency is achieved by performing all necessary processing at the low sampling rate. Moreover the repeated use of a single processing block makes this structure highly modular and eminently suitable for LSI/VLSI implementation. Particular emphasis is placed on decimating and interpolating by a factor of two. The proposed structures offer very desirable properties in addition to the above and, in particular, in relation to their insensitivity with respect to reduced wordlength performance. Sampling-rate alteration by factors other than two is also examined and design procedures are given. The paper contains extensive tables and graphs to facilitate the design of these structures by estimating the required order and parameters for the given requirements before attempting any optimisation. In the case of interpolating by a factor two an analytic equiripple solution is given. The paper includes some design examples with performance evaluation under different wordlengths.