• DocumentCode
    926147
  • Title

    n-user asynchronous arbiter

  • Author

    Corsini, P.

  • Author_Institution
    UniversitÃ\xa0 di Pisa, Dipartimento Sperimentale di, Elettrotecnica ed Elettronica, FacoltÃ\xa0 di Ingegneria, Pisa, Italy
  • Volume
    11
  • Issue
    1
  • fYear
    1975
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter, based on the 2-user perfect asynchronous arbiter of Patil, is structured in a modular way. At every processor, a module is given. The arbiter takes shape by properly interconnecting the modules.
  • Keywords
    computer architecture; parallel processing; computer architecture; concurrent asynchronous processors; n-user asynchronous arbiter; parallel processing;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19750001
  • Filename
    4236507
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=926147