• DocumentCode
    926980
  • Title

    Reliable and efficient system-on-chip design

  • Author

    Shanbhag, Naresh R.

  • Author_Institution
    Illinois Univ., Urbana, IL, USA
  • Volume
    37
  • Issue
    3
  • fYear
    2004
  • fDate
    3/1/2004 12:00:00 AM
  • Firstpage
    42
  • Lastpage
    50
  • Abstract
    To increase processor performance, the microprocessor industry is scaling feature sizes into the deep submicron and sub-100-nanometer regime. The recent emergence of noise and the dramatic increase in process variations have raised serious questions about using nanometer process technologies to design reliable, low-power, high-performance computing systems. The design and electronic design automation communities must work closely with the process engineering community to address these problems. Specifically, researchers must explore the tradeoffs between reliability and energy efficiency at the device, circuit, architectural, algorithmic, and system levels.
  • Keywords
    electronic design automation; microprocessor chips; performance evaluation; power consumption; semiconductor device noise; system-on-chip; electronic design automation; energy efficiency; high-performance computing systems; low-power computing systems; microprocessor industry; nanometer process technologies; noise; process engineering; processor performance; reliable system-on-chip design; Circuit noise; Electronic design automation and methodology; Microprocessors; Noise level; Phase noise; Power system reliability; Semiconductor device noise; Signal processing; System-on-a-chip; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Computer
  • Publisher
    ieee
  • ISSN
    0018-9162
  • Type

    jour

  • DOI
    10.1109/MC.2004.1274003
  • Filename
    1274003