DocumentCode
927008
Title
Making typical silicon matter with Razor
Author
Austin, Todd ; Blaauw, David ; Mudge, Trevor ; Flautner, Krisztián
Author_Institution
Michigan Univ., MI, USA
Volume
37
Issue
3
fYear
2004
fDate
3/1/2004 12:00:00 AM
Firstpage
57
Lastpage
65
Abstract
Voltage scaling has emerged as a powerful technology for addressing the power challenges that current on-chip densities pose. Razor is a voltage-scaling technology based on dynamic, in-situ detection and correction of circuit-timing errors. Razor permits design optimizations that tune the energy in a microprocessor pipeline to typical circuit-operational levels. This eliminates the voltage margins that traditional worst-case design methodologies require and lets digital systems run correctly and robustly at the edge of minimum power consumption. Occasional heavyweight computations may fail and require additional time and energy for recovery, but the optimized pipeline requires significantly less energy overall than traditional designs.
Keywords
circuit optimisation; error correction; error detection; hardware-software codesign; logic CAD; microprocessor chips; pipeline processing; power consumption; timing; Razor; circuit-timing error correction; circuit-timing error detection; codesign methodology; design optimizations; digital systems; microprocessor pipeline; minimum power consumption; on-chip densities; timing speculation; voltage scaling; Design methodology; Design optimization; Digital systems; Dynamic voltage scaling; Error correction; Microprocessors; Pipelines; Robustness; Silicon; Tuned circuits;
fLanguage
English
Journal_Title
Computer
Publisher
ieee
ISSN
0018-9162
Type
jour
DOI
10.1109/MC.2004.1274005
Filename
1274005
Link To Document