• DocumentCode
    927164
  • Title

    A new two-mode channel FET (TMT) for super-low-noise and high-power applications

  • Author

    Sawada, Minoru ; Inoue, Daijiro ; Matsumura, Kohji ; Harada, Yasoo

  • Author_Institution
    Sanyo Electric Co. Ltd., Osaka, Japan
  • Volume
    14
  • Issue
    7
  • fYear
    1993
  • fDate
    7/1/1993 12:00:00 AM
  • Firstpage
    354
  • Lastpage
    356
  • Abstract
    A super-low-noise two-mode channel FET (TMT) with high- and plateau-shaped transconductance (g/sub m/) characteristics has been developed. It has two electron transport modes against the applied gate voltage (V/sub gs/). That is, the electrons mainly drift in a highly doped channel region at a shallow V/sub gs/. A plateau g/sub m/ region and the maximum g/sub m/ were achieved at a V/sub gs/ range of -0.25 approximately +0.5 V and 535 mS/mm, respectively. The minimum noise figure and associated gain for the TMT were superior in the low-drain-current (I/sub ds/) region and nearly equal in the middle and high I/sub ds/ region to those of an AlGaAs/InGaAs pseudomorphic HEMT fabricated using the same wafer process and device geometry.<>
  • Keywords
    III-V semiconductors; aluminium compounds; field effect transistors; gallium arsenide; indium compounds; power transistors; semiconductor device noise; solid-state microwave devices; -0.25 to 0.5 V; 535 mS/mm; AlGaAs-GaAs-InGaAs; MBE; MMIC application; TMT gain; applied gate voltage; device geometry; electron transport modes; noise figure; plateau-shaped transconductance; semiconductor; super-low noise FET; two-mode channel FET; wafer process; Electrons; FETs; Geometry; Indium gallium arsenide; Noise figure; PHEMTs; Transconductance; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/55.225571
  • Filename
    225571