VDS voltage capabilities of a diffused j.f.e.t. with a vertical-channel arrangement

In the letter, it is shown that the VDS voltage limitation in a j.f.e.t. with a vertical-channel arrangement in the off state is due, not to the breakdown voltage of the gate-drain junction, as for a classical j.f.e.t., but to the field-effect lowering of the potential barrier created in the channel by the polarisation of the gate. The analysis is based on the 2-dimensional numerical solution of the general semiconductor equations.