Test scheduling and control for VLSI built-in self-test

Author

Craig, Gary L. ; Kine, C.R. ; Saluja, Kewal K.

Author_Institution

Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA

Volume

37

Issue

9

fYear

1988

fDate

9/1/1988 12:00:00 AM

Firstpage

1099

Lastpage

1109

Abstract

The test scheduling problem for equal length and unequal length tests for VLSI circuits using built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from C. Kime and K. Saluja (1982) is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed for defining test schedules for both the equal length test and unequal length test cases. For the unequal length test case, three different scheduling disciplines are defined, and scheduling algorithms are given for two of the three cases. Data on algorithm performance are presented. The issue of the control of the test schedule is also addressed, and a number of structures are proposed for implementation of control

Keywords

VLSI; automatic testing; integrated circuit testing; scheduling; BIST; VLSI; algorithm performance; built-in self-test; equal length test; hierarchical model; suboptimum algorithms; test resource sharing; test scheduling; unequal length test; Automatic testing; Built-in self-test; Circuit testing; Compressors; Logic testing; Parallel processing; Pattern analysis; Scheduling algorithm; Test pattern generators; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.2260

Filename

2260