Part 1: VLSI implementation of an optimised hierarchical multiplier

The implementation and optimisation procedure of a regular, and recursive, high-speed N-bit multiplier design is presented. The design comprises two simple cells: a 2 × 2-bit multiplier PLA and a full adder PLA, and most of the interconnections are local and regular. Extension of the design to any multiplier word size can be done by simply combining smaller cell blocks following the same algorithm. The multiplier is optimised for area-time complexity, using the analysis presented in Part 2, and its performance relative to previously reported designs is good. A four-bit multiplier implementation is discussed in detail.