• DocumentCode
    928142
  • Title

    Efficient testing of optimal time adders

  • Author

    Becker, Bernd

  • Author_Institution
    Angewandte Math. und Inf., Univ. des Saarlandes, Saarbrucken, West Germany
  • Volume
    37
  • Issue
    9
  • fYear
    1988
  • fDate
    9/1/1988 12:00:00 AM
  • Firstpage
    1113
  • Lastpage
    1121
  • Abstract
    Considers the design of two well-known optimal time adders: the carry look-ahead adder and the conditional sum adder. It is shown that 6 log2(n)-4 and 6 log2(n)+2 test patterns suffice to completely test the n-bit carry look-ahead adder and the n-bit conditional sum adder with respect to the single stuck-at fault model (for a given set of basic cells). The results are considered pertinent to establishing the correct behavior of a given VLSI chip
  • Keywords
    VLSI; adders; integrated logic circuits; logic testing; VLSI chip; carry look-ahead adder; conditional sum adder; optimal time adders; Adders; Circuit faults; Circuit testing; Digital arithmetic; Electrical fault detection; Fault detection; Logic arrays; Logic testing; Tree data structures; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.2262
  • Filename
    2262
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=928142