DocumentCode :
928540
Title :
A planar interconnection technology utilizing the selective deposition of tungsten-multilevel implementation
Author :
Thomas, David C. ; Wong, S. Simon
Author_Institution :
Sch. of Electr. Eng., Cornell Univ., Ithaca, NY
Volume :
39
Issue :
4
fYear :
1992
fDate :
4/1/1992 12:00:00 AM
Firstpage :
901
Lastpage :
907
Abstract :
The increases in crosstalk disturbance, signal delay, and current density as interconnections are scaled have been examined through simulations. Interconnections will greatly degrade the performance of integrated circuits if the metal pitch is reduced to much below 2 μm. An alternative to achieve the continuous demand in increasing the interconnection density is to add multiple layers of metallization. A tungsten interconnection technology, which inherently preserves a flat wafer surface, as well as providing frameless and stacked vias, has been demonstrated. Electrical characterization and limitations of the technology are discussed
Keywords :
crosstalk; current density; delays; integrated circuit technology; metallisation; tungsten; crosstalk disturbance; current density; electrical characterization; flat wafer surface; frameless vias; integrated circuits; interconnection density; metal pitch; multilevel metallization; planar interconnection technology; signal delay; simulations; stacked vias; Chemical technology; Delay; Etching; Fabrication; Filling; Implants; Integrated circuit interconnections; Metallization; Planarization; Tungsten;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.127480
Filename :
127480
Link To Document :
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