Design of very-low-frequency digital oscillators

This paper describes an approach for designing a digital sinusoidal oscillator when the oscillating frequencyf0 is very low with respect to the sampling frequencyfs. The approach is based on the state-variable formalism and a set of conditions that make it easier to find oscillators with minimum coefficient sensitivity. For these situations (f0 «fs) several new digital oscillator structures are presented. The sensitivity to coefficient quantisation and the output noise variance for these structures remain constant and generally insignificant as the ratiof0/fs is increased. Some numerical results are also presented showing the improvements.