DocumentCode
928594
Title
An analytical delayed-turn-off model for buried-channel PMOS devices operating at 77 K
Author
Sim, Jai-hoon ; Kuo, James B.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
39
Issue
4
fYear
1992
fDate
4/1/1992 12:00:00 AM
Firstpage
939
Lastpage
947
Abstract
A closed-formed analytical PMOS delayed-turn-off model suitable for simulation of circuits with buried-channel PMOS devices operating in the delayed-turn-off region at liquid-nitrogen temperature is presented. As verified by low-temperature PISCES results, the closed-form analytical PMOS delayed-turn-off model provides a much better accuracy for simulation of circuits operating at 77 K
Keywords
MOS integrated circuits; electronic engineering computing; insulated gate field effect transistors; semiconductor device models; 77 K; PISCES; analytical delayed-turn-off model; buried-channel PMOS devices; circuit simulation; closed-form model; low-temperature; Analog circuits; Analytical models; Circuit simulation; Delay; Energy states; MOS devices; SPICE; Semiconductor device modeling; Temperature; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.127486
Filename
127486
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